In order to build faster and more complex integrated circuits, semiconductor manufacturers have increased the number of components in the integrated circuit while reducing the overall size of the circuit. The small circuit size requires multiple overlying conductive layers to electrically interconnect the vast number of components within the integrated circuit. As successive layers of conductors and dielectric materials are deposited over previously defined structures, the surface topography can become uneven. To be manufactured reliably, the conductive layers need to be deposited, and an interconnect pattern defined on a smooth, planar surface. A planarization process is typically performed after the deposition of a dielectric passivation layer to reduce the topographic contrast of the passivation layer. A conductive layer is then deposited on a smooth, even surface and the interconnect pattern reliably defined using conventional photolithography.
One method for planarizing the substrate surface during integrated circuit fabrication is a polish planarization process. Recently, polishing processes have been developed which abrasively removed elevated portions of a passivation layer overlying an uneven substrate. In this process, known as chem-mech polishing, the passivated surface of the substrate is brought into contact with a rotating polish pad in the presence of an abrasive slurry. A portion of the passivation layer is then abrasively removed by the mechanical action of the polish pad and the chemical action of the slurry. The slurry serves to lubricate the surface and contains a fill material such as silica to provide additional abrasive force. Additional chemicals are sometimes added to the slurry to adjust the pH and to chemically etch the surface of the layer to be polished. See for example, U.S. Pat. No. 4,910,155 to W. Cote. Wafer polishing has the advantage of being very versatile and not limited by the particular material being polished. The polishing technique can also be used to remove irregularities from the surface of a silicon substrate.
A common requirement of all polishing processes is that the substrate be uniformly polished. In the case of polishing back a passivation layer, it is desirable to polish the layer uniformly from edge to edge on the substrate. To insure that a planar surface is obtained, the passivation layer overlying elevated surface regions must be uniformly removed. Uniform polishing can be difficult because, typically, there is a strong dependence in the polish removal rate with localized variations in the surface topography of the substrate. For example, in substrate areas having a high degree of surface variation, such as areas having closely spaced adjacent trenches, the polishing rate is higher than in areas lacking a high degree of surface contrast, such as areas having large active device regions. The effect of surface topography on the removal rate requires the polishing time to be extended beyond that required to just remove the passivation layer from the most elevated regions. However, the polish time cannot be extended indefinitely or layers underlying the passivation layer can be damaged. The polish selectivity can be defined as the ratio of the removal rate of an overlying layer to that of an underlying layer. The polish selectivity must be maximized in order to improve the edge to edge polish rate uniformity and the ultimate ability of the polish process to form a planar surface. One technique used to increase polishing selectivity, described in U.S. Pat. No. 4,944,836 to K. Beyer, adjusts the composition and pH of the slurry solution depending upon the polish characteristics of the particular material to be polished and the underlying layer. More commonly, a hard, thin film referred to as a polish stop layer is deposited to overlie the uneven surface of the substrate prior to depositing the passivation layer. The polish stop layer underlying the passivation layer is more resistant to abrasive removal than the passivation layer. During polishing, when the polish stop overlying the most elevated surface regions of the substrate is exposed, the removal rate of material from the substrate declines and ideally stops altogether as all of the elevated portions of the polish stop layer become exposed. If the polish stop material is sufficiently resistant to abrasive removal and chemically unreactive with the components in the slurry, the polishing time can be extended for a long enough period to uniformly polish the passivation layer without damaging underlying layers.
While potentially offering wide versatility and a high degree of uniformity, the polish process must be controlled to avoid damaging underlying layers. Although previous investigators have adjusted various elements of the polishing process to increase the polish selectivity, such as the slurry composition and the polish pad material, the preferred method remains the use of a polish stop layer. A variety of polish stop materials have been reported including silicon nitride, alumina and magnesium oxide with silicon nitride being the most widely used. For example, the use of silicon nitride is described in U.S. Pat. No. 4,671,851 to K. Beyer et al. The polish stop material must be chemically inert, have high hardness and have deposition and removal characteristics which are compatible with existing process techniques. While materials such as silicon nitride and alumina are well characterized and widely used in semiconductor fabrication, they lack the necessary characteristics needed for a highly selective polish process.